Today, electronic devices commonly use non-volatile memory storage devices to store massive amounts of data. For example, cell phones have the capability of obtaining and storing images that can be transferred to other devices. Such information can be stored in one or more non-volatile memory devices. To process and store such information, these types of storage devices constantly require programming and erasing of memory bits in memory cell arrays. A common non-volatile memory is a charge trapping memory, which is capable of storing two bits in a memory cell.
FIG. 1 illustrates a simple cross-section of a memory cell 100 for a prior charge trapping memory device. The charge trapping memory cell 100 includes a thin oxide-nitride-oxide (ONO) layer 110 over a source 120, a drain 130, and a channel 140 layer. A gate layer 150 is formed over the ONO layer 110. This cell can form a metal oxide silicon field effect transistor (MOSFET). Accordingly, for memory cell 100, data can be stored in the form of charge trapped in the ONO layer 110 over edges of the channel layer 140 that form part of a MOSFET. Programming of the charge trapping memory cell 100 can be performed by injecting channel hot electrons (CHE) into the ONO layer 110. Erasing can be performed by band-to-band-generated tunnel-assisted hot hole injection (HHI) into the ONO layer 110. To read the data stored in memory cell 100, a charge stored in the ONO layer 110 can be read by sensing the current from the drain and source when their roles are reversed relative to a programming operation. Because charge can be stored in the ONO layer 110 at both junction edges of the channel layer 140, the memory cell 100 can store two bits of data.
The transistor associated with the memory cell 100 has a threshold voltage that allows charge carriers, such as holes or electrons, from the channel layer 140 to move into the ONO layer 110. During a program operation, when electrons are injected into the memory cell 100, the threshold voltage of the memory cell 100 rises. On the other hand, during an erase operation, when holes are injected, electrons or negative charge carriers are reduced and the threshold voltage of the memory cell 100 falls. FIG. 2 illustrates a schematic diagram of threshold voltage distribution of a bit for the prior charge trapping memory cell 100 with respect to a cycle including a program and erase operation. The horizontal axis represents threshold voltage Vt distribution and the vertical axis represents cycles in logarithmic scale. Referring to FIG. 2, for the program phase, the memory device begins with a low Vt distribution for memory cells that goes to a high Vt distribution. Conversely, for the erase program phase, the memory device decreases the threshold voltage level for the memory cells, which goes from the high Vt distribution back to the low Vt distribution (due to decrease in electrons or negative charge carriers). EV refers to the voltage level for erase verifying of a bit of the charge trapping memory cell. PV refers to the voltage level program verifying of a bit of the charge trapping memory cell, and RD refers to the voltage level for reading of a bit of the charge trapping memory cell.
There are a number of drawbacks with the prior charge trapping memory device that performs the erase operation using the hot hole injection HHI technique. This technique is susceptible to hot-hole charge trapping in the ONO layer that induces room temperature (RT) drift and charge loss, all of which results in threshold voltage fluctuation. RT drift arises because of the sensitivity of memory cells to room temperature that causes the threshold voltage of two-bit charge trapping memory cells to drift during an erase. This drift can deteriorate the reliability of data stored in the memory cells. Charge loss or retention loss changes the threshold voltage over time for a bit of a memory cell. The threshold voltage Vt of the cell can change due to redistribution of trapped charge in the ONO layer. This can lead to read error.
Thus, what is needed is an improved non-volatile memory device that overcomes the above drawbacks during an erase operation.